LAN8187_06 Datasheet, PDF (15/72 Pages) SMSC Corporation – ±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWRTM

±15kV ESD Protected MII/RMII Fast-Ethernet PHY with HP Auto-MDIX and SMSC flexPWR^TM
Datasheet
Table 3.4 Boot Strap Configuration Inputs^a
SIGNAL NAME
TYPE
DESCRIPTION
MODE2
MODE1
MODE0
REG_EN
AMDIX_EN
I
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 53, for
the MODE options.
I
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 53, for
the MODE options.
I
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page 53, for
the MODE options.
I
Regulator Enable: Internal +1.8V regulator enable:
VDDIO – Enables internal regulator.
VSS– Disables internal regulator.
I
HP Auto-MDIX Enable: This pin is used to manualy disable the
HP Auto-MDIX function. This can be bypassed using the internal
register 27 bit 15. Please see Table 4.3, “Auto-MDIX Control,” on
page 30 for more information.
(VDDIO or Floating) – Enables HP Auto-MDIX.
VSS – Disables HP Auto-MDIX
CH_SELECT
I
Channel Select: This pin is used in conjunction with the
AMDIX_EN pin above to manualy select the channel to transmit
and receive on. For more information please see Table 4.3,
“Auto-MDIX Control,” on page 30
(VDDIO or Floating) – MDIX - TX pair receives RX pair transmits.
0V – MDI -TX pair transmits RX pair receives.
GPO0/RMII
I/O General Purpose Output 0 – General Purpose Output signal.
Driven by bits in registers 27 and 31.
RMII – MII/RMII mode selection is latched on the rising edge of
the internal reset (nreset) based on the following strapping:
Float the GPO0 pin for MII mode or pull-high with an external
Pull-up resistor (see Table 4.4, “Boot Strapping Configuration
Resistors,” on page 32) to VDDIO to set the device in RMII
mode.
Note: See Section 4.6.3, "MII vs. RMII Configuration," on
page 26 for more details.
a.On nRST transition high, the PHY latches the state of the configuration pins in this table.
SIGNAL NAME
nINT
nRST
Revision 1.0 (12-14-06)
Table 3.5 General Signals
TYPE
I/O
I
DESCRIPTION
LAN Interrupt – Active Low output. Place a pull-up external
resistor (see Table 4.4, “Boot Strapping Configuration Resistors,”
on page 32) to VCC 3.3V.
Notes:
„ This signal is mux’d with TX_ER/TXD4
„ See Section 4.10, "(TX_ER/TXD4)/nINT Strapping," on
page 31 for additional details on Strapping options.
External Reset – input of the system reset. This signal is active
LOW.
15
DATASHEET
SMSC LAN8187/LAN8187I