SI5326 Datasheet, PDF (9/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Pin # Pin Name I/O Signal Level
Description
19
DEC
I
LVCMOS Latency Decrement.
A pulse on this pin decreases the input to output device latency by
1/f_OSC (approximately 200 ps). There is no limit on the range of
latency adjustment by this method.
Pin control is enabled by setting INCDEC_PIN = 1. If
INCDEC_PIN = 0, this pin is ignored and output latency is con-
trolled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled and
the device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch.
This pin has a weak pull-down.
20
INC
I
LVCMOS Latency Increment.
A pulse on this pin increases the input to output device latency by
1/f_OSC (approximately 200 ps). There is no limit on the range of
latency adjustment by this method.
Pin control is enabled by setting INCDEC_PIN = 1. If
INCDEC_PIN = 0, this pin is ignored and output latency is con-
trolled via the CLAT register.
If both INC and DEC are tied high, phase buildout is disabled and
the device maintains a fixed-phase relationship between the
selected input clock and the output clock during an input clock
switch.
This pin has a weak pull-down.
21
CS_CA I/O LVCMOS Input Clock Select/Active Clock Indicator.
In manual clock selection mode, this pin functions as the manual
input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1.
1 = Select CKIN2.
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this func-
tion and this input tristates.
In automatic clock selection mode, this pin indicates which of the
two input clocks is currently the active clock. If alarms exist on both
clocks, CK_ACTV will indicate the last active clock that was used
before entering the digital hold state. The CK_ACTV_PIN register
bit must be set to 1 to reflect the active clock status to the
CK_ACTV output pin.
0 = CKIN1 active input clock.
1 = CKIN2 active input clock.
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status
will always be reflected in the CK_ACTV_REG read only register
bit.
This pin has a weak pull-down.
22
SCL
I
LVCMOS Serial Clock/Serial Clock.
This pin functions as the serial clock input for both SPI and I²C
modes.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map.
Confidential Rev. 0.2
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