SI5326 Datasheet, PDF (1/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
PRELIMINARY DATA SHEET
ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR
Description
The Si5326 is a jitter-attenuating precision clock multiplier for
applications requiring sub 1 ps jitter performance. The Si5326
accepts dual clock inputs ranging from 2 kHz to 710 MHz and
generates two clock outputs ranging from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz. The two outputs are
divided down separately from a common source. The device
provides virtually any frequency translation combination
across this operating range. The Si5326 input clock
frequency and clock multiplication ratio are programmable
through an I²C or SPI interface. The Si5326 is based on
Silicon Laboratories' 3rd-generation DSPLL^® technology,
which provides any-rate frequency synthesis and jitter
attenuation in a highly integrated PLL solution that eliminates
the need for external VCXO and loop filter components. The
DSPLL loop bandwidth is digitally programmable, providing
jitter performance optimization at the application level.
Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5326
is ideal for providing clock multiplication and jitter attenuation
in high performance timing applications.
Applications
SONET/SDH OC-48/OC-192 line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Optical modules
Wireless basestations
Data converter clocking
xDSL
SONET/SDH + PDH clock synthesis
Test and measurement
Features
Generates any frequency from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz from an input
frequency of 2 kHz to 710 MHz
Ultra-low jitter clock outputs w/jitter generation as
low as 0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Dual clock inputs w/manual or automatically
controlled hitless switching
Dual clock outputs with selectable signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom FEC ratios
(255/238, 255/237, 255/236)
LOL, LOS, FOS alarm outputs
Digitally-controlled output phase adjust
I²C or SPI programmable
On-chip voltage regulator for 1.8, 2.5, or 3.3 V
±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Xtal or Refclock
CKIN1
CKIN2
Loss of Signal/
Frequency Offset
Loss of Lock
÷ N31
÷ N32
DSPLL^®
÷ N2
÷ NC1
÷ NC2
Signal Detect
Control
I²C/SPI Port
Device Interrupt
Rate Select
Clock Select
Latency Control
CKOUT1
CKOUT2
VDD (1.8, 2.5, or 3.3 V)
GND
Confidential Rev. 0.2 2/07
Copyright © 2007 by Silicon Laboratories
Si5326
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.