SI5326 Datasheet, PDF (3/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

Si5326
Table 1. Performance Specifications (Continued)
(V_DD = 1.8, 2.5, or 3.3 V ±10%, T_A = –40 to 85 ºC)
Parameter
Symbol
Test Condition
Min
Typ
Max Unit
Duty Cycle
PLL Performance
CKO_DC
45
—
55
%
Jitter Generation
J_GEN
f_OUT = 622.08 MHz,
—
LVPECL output format
50 kHz–80 MHz
0.3
TBD ps rms
12 kHz–20 MHz
—
0.3
TBD ps rms
800 Hz–80 MHz
—
TBD
TBD ps rms
Jitter Transfer
External Reference Jitter
Transfer
Phase Noise
J_PK
J_PKEXTN
CKO_PN
f_OUT = 622.08 MHz
100 Hz offset
—
0.05
0.1
dB
—
TBD
TBD
dB
—
TBD
TBD dBc/Hz
1 kHz offset
—
TBD
TBD dBc/Hz
10 kHz offset
—
TBD
TBD dBc/Hz
100 kHz offset
—
TBD
TBD dBc/Hz
1 MHz offset
—
TBD
TBD dBc/Hz
Subharmonic Noise
SP_SUBH Phase Noise @ 100 kHz Off- —
set
TBD
TBD
dBc
Spurious Noise
SP_SPUR
Max spur @ n x F3
—
(n > 1, n x F3 < 100 MHz)
TBD
TBD
dBc
Package
Thermal Resistance
Junction to Ambient
Theta JA
Still Air
—
TBD
—
ºC/W
Note: For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate Precision
Clock Family Reference Manual. This document can be downloaded from www.silabs.com/timing.
Table 2. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
LVCMOS Input Voltage
Operating Junction Temperature
Storage Temperature Range
ESD HBM Tolerance (100 pF, 1.5 kΩ)
V_DD
–0.5 to 3.6
V
V_DIG
–0.3 to (V_DD + 0.3)
V
T_JCT
–55 to 150
ºC
T_STG
–55 to 150
ºC
2
kV
ESD MM Tolerance
200
V
Latch-Up Tolerance
JESD78 Compliant
Note: Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum
rating conditions for extended periods of time may affect device reliability.
Confidential Rev. 0.2
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