SI5326 Datasheet, PDF (7/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

2. Pin Descriptions: Si5326
Si5326
36 35 34 33 32 31 30 29 28
RST 1
27 SDI
NC 2
26 A2_SS
INT_C1B 3
25 A1
C2B 4
VDD 5
XA 6
GND
Pad
24 A0
23 SDA_SDO
22 SCL
XB 7
21 _{CS_CA}
GND 8
20 INC
NC 9
19 DEC
10 11 12 13 14 15 16 17 18
Pin numbers are preliminary and subject to change.
Pin # Pin Name I/O Signal Level
Description
1
RST
I
LVCMOS External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device reg-
isters to their default value. Clock outputs are tristated during reset.
After rising edge of RST signal, the Si5326 will perform an internal
self-calibration.
This pin has a weak pull-up.
2, 9, 14,
NC
—
30, 33
—
No Connect.
This pin must be left unconnected for normal operation.
3
INT_C1B O LVCMOS Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm output
for CKIN1. If used as an interrupt output, INT_PIN must be set to 1.
The pin functions as a maskable interrupt output with active polar-
ity controlled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS (and option-
ally FOS) alarm indicator for CKIN1. Set CK1_BAD_PIN = 1 and
INT_PIN = 0.
0 = CKIN1 present.
1 = LOS (FOS) on CKIN1.
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5326 Register Map.
Confidential Rev. 0.2
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