SI5326 Datasheet, PDF (15/16 Pages) Silicon Laboratories – ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR

DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated LVTTL to LVCMOS is Table 2, “Absolute
Maximum Ratings,” on page 3.
Added Figure 1, “Typical Phase Noise Plot,” on page
4.
Updated Figure 2, “Si5326 Typical Application
Circuit (I²C Control Mode),” and Figure 3, “Si5326
Typical Application Circuit (SPI Control Mode),” on
page 5 to show preferred external reference
interface.
Updated “2. Pin Descriptions: Si5326”.
Added RATE0 and changed RATE to RATE1 and
expanded RATE[1:0] description.
Changed font of register names to underlined italics.
Updated "3. Ordering Guide" on page 11.
Added "4. Package Outline: 36-Pin QFN" on page
12.
Added “5. Recommended PCB Layout”.
Si5326
Confidential Rev. 0.2
15