SI516 Datasheet, PDF (9/22 Pages) Silicon Laboratories – DUAL FREQUENCY VOLTAGE-CONTROLLED

Si516
Table 7. Output Clock Jitter and Phase Noise (HCSL)
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = HCSL
Parameter
Period Jitter
(RMS)
Period Jitter
(Pk-Pk)
Phase Jitter
(RMS)
Symbol
Test Condition
Min
JPRMS
10k samples^*
—
JPPKPK
10k samples^*
—
φJ
1.875 MHz to 20 MHz integration
—
bandwidth^*(brickwall)
Phase Noise,
156.25 MHz
12 kHz to 20 MHz integration band-
—
width^* (brickwall)
φN
100 Hz
—
1 kHz
—
10 kHz
—
100 kHz
—
Spurious
1 MHz
—
SPR
LVPECL output, 156.25 MHz,
—
offset>10 kHz
*Note: Applies to an output frequency of 100 MHz.
Typ
—
—
0.25
0.8
–75
–98
–117
–127
–136
–75
Max
1.2
11
0.30
Unit
ps
ps
ps
1.0
ps
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc
Rev. 1.0
9