SI516 Datasheet, PDF (21/22 Pages) Silicon Laboratories – DUAL FREQUENCY VOLTAGE-CONTROLLED

DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0
 Updated Table 1 on page 4.
Updates to supply current typical and maximum values
for CMOS, LVDS, LVPECL and HCSL.
CMOS frequency test condition corrected to 100 MHz.
Updates to OE VIH minimum and VIL maximum values.
 Updated Table 3 on page 5.
Dual CMOS nominal frequency maximum added.
Disable time maximum values updated.
Enable time parameter added.
 Updated Table 4 on page 6.
CMOS output rise / fall time typical and maximum
values updated.
LVPECL/HCSL output rise / fall time maximum value
updated.
LVPECL output swing maximum value updated.
LVDS output common mode typical and maximum
values updated.
HCSL output swing maximum value updated.
Duty cycle minimum and maximum values tightened to
48/52%.
 Updated Table 5 on page 7.
Phase jitter test condition, typical and maximum value
updated.
Phase noise typical values updated.
Additive RMS jitter due to external power supply noise
typical values updated.
 Added Tables 6, 7, 8 for LVDS, HCSL, CMOS and
Dual CMOS operations.
 Added note to Figure 2 clarifying CMOS and Dual
CMOS maximum frequency.
 Updated Figure 5 outline diagram to correct pinout.
 Updated “8. Top Marking” section and moved to
page 20.
Si516
Rev. 1.0
21