SI516 Datasheet, PDF (7/22 Pages) Silicon Laboratories – DUAL FREQUENCY VOLTAGE-CONTROLLED

Si516
Table 5. Output Clock Jitter and Phase Noise (LVPECL)
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = LVPECL
Parameter
Period Jitter (RMS)
Period Jitter (PK-PK)
Phase Jitter (RMS)
Symbol
Test Condition
Min
J_PRMS
10 k samples¹
—
J_PPKPK
10 k samples¹(brickwall)
—
φJ
12 kHz to 20 MHz² (brickwall)
—
1.875 MHz to 20 MHz² (brickwall) —
Phase Noise, 155.52 MHz
φN
100 Hz offset
—
1 kHz offset
—
10 kHz offset
—
100 kHz offset
—
1 MHz offset
—
Additive RMS Jitter Due to J_PSRR
100 kHz sinusoidal noise
—
External Power Supply
Noise³
200 kHz sinusoidal noise
—
500 kHz sinusoidal noise
—
1 MHz sinusoidal noise
—
Spurious Performance
SPR
F_O = 156.25 MHz,
—
Offset > 10 kHz
Typ
—
—
0.9
0.25
–71
–94
–113
–124
–136
4.0
3.5
3.5
3.5
–75
Max Unit
1.3
ps
11
ps
1.3
ps
0.5
ps
— dBc/Hz
— dBc/Hz
— dBc/Hz
— dBc/Hz
— dBc/Hz
—
ps
—
ps
—
ps
—
ps
—
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to spurs introduced by sinewave noise added to VDD (100 mV_PP).
Rev. 1.0
7