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SI516 Datasheet, PDF (6/22 Pages) Silicon Laboratories – DUAL FREQUENCY VOLTAGE-CONTROLLED | |||
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Si516
Table 4. Output Clock Levels and Symmetry
VDD = 2.5 or 3.3 V ±10%, TA = â40 to +85 oC
Parameter
Symbol Test Condition
Min
CMOS Output Logic High
VOH
CMOS Output Logic Low
VOL
CMOS Output Logic High
IOH
Drive
3.3 V
2.5 V
0.85 x VDD
â
â8
â6
CMOS Output Logic Low
IOL
3.3 V
8
Drive
2.5 V
6
CMOS Output Rise/Fall Time TR/TF
0.1 to 125 MHz,
â
(20 to 80% VDD)
CL = 15 pF
0.1 to 212.5 MHz,
â
CL = no load
LVPECL/HCSL Output
TR/TF
â
Rise/Fall Time
(20 to 80% VDD)
LVDS Output Rise/Fall Time TR/TF
â
(20 to 80% VDD)
LVPECL Output Common
VOC
50 ï to VDD â 2 V,
â
Mode
single-ended
LVPECL Output Swing
VO
50 ï to VDD â 2 V,
0.55
single-ended
LVDS Output Common Mode VOC
100 ï line-line,
1.13
VDD = 3.3/2.5 V
LVDS Output Swing
VO
Single-ended 100 ï
0.25
differential termination
HCSL Output Common Mode VOC
50 ïï to ground
0.35
HCSL Output Swing
VO
Single-ended
0.58
Duty Cycle
DC
48
Typ
â
â
â
â
â
â
0.8
0.6
â
â
VDD â
1.4 V
0.8
1.23
0.38
0.38
0.73
50
Max
â
0.15 x VDD
â
â
â
â
1.2
Unit
V
V
mA
mA
mA
mA
ns
0.9
ns
565
ps
800
â
0.90
1.33
0.42
0.42
0.85
52
ps
V
VPPSE
V
VPPSE
V
VPPSE
%
6
Rev. 1.0
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