SI516 Datasheet, PDF (5/22 Pages) Silicon Laboratories – DUAL FREQUENCY VOLTAGE-CONTROLLED

Si516
Table 2. Vc Control Voltage Input
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC
Parameter
Control Voltage Range
Control Voltage Tuning Slope
(10 to 90% V_DD)
Kv Variation
Symbol
V_C
Kv
Kv_var
Control Voltage Linearity
L_VC
Modulation Bandwidth
BW
Vc Input Impedance
Z_VC
Test Condition
Ordering option
BSL
Min
Typ
Max
0.1 x V_DD V_DD/2 0.9 x V_DD
60, 90, 120, 150
Unit
V
ppm/V
—
—
±10
%
–5
±1
+5
%
—
10
—
kHz
—
100
—
k
Table 3. Output Clock Frequency Characteristics
V_DD = 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC
Parameter
Symbol
Test Condition
Nominal Frequency
Temperature Stability
Aging
F_O
CMOS, Dual CMOS
F_O
LVDS/LVPECL/HCSL
S_T
T_A = –40 to +85 ^oC
A Frequency drift over 10-year life
Minimum Absolute Pull Range APR
Ordering option
Startup Time
Disable Time
Enable Time
Settling Time after FS Change
T_SU
T_D
T_D
t_FRQ
Minimum V_DD until output fre-
quency (F_O) within specification
F_O > 10 MHz
F_O < 10 MHz
F_O > 10 MHz
F_O < 10 MHz
Min Typ Max
0.1
— 212.5
0.1
—
250
–20
—
+20
—
—
±8.5
±30, ±50,±80, ±100
—
—
10
—
—
5
—
—
40
—
—
20
—
—
60
—
—
10
Unit
MHz
MHz
ppm
ppm
ppm
ms
µs
µs
µs
µs
ms
Rev. 1.0
5