SI512-13 Datasheet, PDF (9/20 Pages) Silicon Laboratories – Two selectable output frequencies

Si512/513
Table 6. Output Clock Jitter and Phase Noise (HCSL)
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = HCSL
Parameter
Symbol
Test Condition
Min
Period Jitter
JPRMS
10k samples^*
—
(RMS)
Period Jitter
JPPKPK
10k samples^*
—
(Pk-Pk)
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
—
bandwidth^*(brickwall)
12 kHz to 20 MHz integration band-
—
width^* (brickwall)
Phase Noise,
φN
100 Hz
—
156.25 MHz
1 kHz
—
10 kHz
—
100 kHz
—
1 MHz
—
Spurious
SPR
LVPECL output, 156.25 MHz,
—
offset>10 kHz
*Note: Applies to an output frequency of 100 MHz.
Typ
—
—
0.25
0.8
–90
–112
–120
–127
–140
–75
Max
Unit
1.2
ps
11
ps
0.30
ps
1.0
ps
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc/Hz
—
dBc
Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS)
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = CMOS, Dual CMOS
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
—
0.25
0.35
ps
bandwidth² (brickwall)
12 kHz to 20 MHz integration
bandwidth² (brickwall)
—
0.8
1.0
ps
Phase Noise,
φN
156.25 MHz
100 Hz
1 kHz
—
–86
—
dBc/Hz
—
–108
—
dBc/Hz
10 kHz
—
–115
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
1 MHz
—
–136
—
dBc/Hz
Spurious
SPR
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–75
—
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Rev. 1.0
9