SI512-13 Datasheet, PDF (5/20 Pages) Silicon Laboratories – Two selectable output frequencies

Si512/513
Table 2. Output Clock Frequency Characteristics
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC
Parameter
Symbol
Test Condition
Min
Typ
Max Units
Nominal Frequency
F_O
CMOS, Dual CMOS
0.1
—
212.5 MHz
F_O
LVDS/LVPECL/HCSL
0.1
—
250
MHz
Total Stability*
Frequency Stability Grade C
–30
+30
ppm
Frequency Stability Grade B
–50
+50
ppm
Frequency Stability Grade A
–100
+100 ppm
Temperature Stability
Frequency Stability Grade C
–20
+20
ppm
Frequency Stability Grade B
–25
+25
ppm
Frequency Stability Grade A
–50
+50
ppm
Startup Time
T_SU
Minimum V_DD to output
—
—
10
ms
frequency (F_O) within specification
Disable Time
T_D
F_O 10 MHz
—
—
5
µs
F_O < 10 MHz
—
—
40
µs
Enable Time
T_E
F_O 10 MHz
—
—
20
µs
F_O < 10 MHz
—
—
60
µs
Settling Time after FS
Change
t_FRQ
—
—
10
ms
*Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and
vibration (not under operation), and 10 years aging at 40 ^°C.
Rev. 1.0
5