SI512-13 Datasheet, PDF (11/20 Pages) Silicon Laboratories – Two selectable output frequencies

Si512/513
2. Pin Descriptions
FS 1
6 VDD
OE 2
5 NC
GND 3
4 CLK
Si512 CMOS
OE 1
6 VDD
FS 2
5 NC
GND 3
4 CLK
Si513 CMOS
FS 1
6
VDD
OE 2
5 CLK–
GND 3
4 CLK+
Si512 LVDS/LVPECL/
HCSL/ Dual CMOS*
OE 1
6 VDD
FS 2
5 CLK–
GND 3
4 CLK+
Si513 LVDS/LVPECL/
HCSL/Dual CMOS*
*Note: Supports integrated 1:2 CMOS buffer. See section 2.1 “2.1. Dual CMOS Buffer” and section 3 “3. Ordering Information”.
Table 11. Si512 Pin Descriptions (CMOS, OE Pin 2)
Pin
Name
CMOS Function
1
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
2
OE
Output Enable. Internal pull-up for OE active high. Pull-
down for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4
CLK
Clock Output.
5
NC
No connect. Make no external connection to this pin.
6
V_DD
Power Supply Voltage.
Table 12. Si513 Pin Descriptions (CMOS, OE Pin 1)
Pin
Name
CMOS Function
1
OE
Output Enable. Internal pull-up for OE active high. Pull-
down for OE active low. See ordering information.
2
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
3
GND
Electrical and Case Ground.
4
CLK
Clock Output.
5
NC
No connect. Make no external connection to this pin.
6
V_DD
Power Supply Voltage.
Table 13. Si512 Pin Descriptions (OE Pin 2)
Pin
Name
LVPECL/LVDS/HCSL/Dual CMOS Function
1
FS
Frequency Selected.
0 = First frequency selected.
1 = Second frequency selected.
2
OE
Output Enable. Internal pull-up for OE active high. Pull-
down for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6
V_DD
Power Supply Voltage.
Rev. 1.0
11