SI512-13 Datasheet, PDF (6/20 Pages) Silicon Laboratories – Two selectable output frequencies

Si512/513
Table 3. Output Clock Levels and Symmetry
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC
Parameter
Symbol
Test Condition
Min
CMOS Output Logic
V_OH
High
CMOS Output Logic
V_OL
Low
CMOS Output Logic
I_OH
High Drive
3.3 V
2.5 V
0.85 x V_DD
—
–8
–6
1.8 V
–4
CMOS Output Logic
I_OL
3.3 V
8
Low Drive
2.5 V
6
1.8 V
4
CMOS Output Rise/Fall ^T_R^/T_F
0.1 to 125 MHz,
—
Time
C_L = 15 pF
(20 to 80% V_DD)
0.1 to 212.5 MHz,
—
C_L = no load
LVPECL/HCSL Output ^T_R^/T_F
—
Rise/Fall Time
(20 to 80% V_DD)
LVDS Output Rise/Fall ^TR^/TF
—
Time
(20 to 80% V_DD)
LVPECL Output
V_OC
50  to V_DD – 2 V,
—
Common Mode
single-ended
LVPECL Output Swing
V_O
50  to V_DD – 2 V,
0.55
single-ended
LVDS Output Common
Mode
V_OC 100  line-line, V_DD = 3.3/2.5 V
100  line-line, V_DD = 1.8 V
1.13
0.83
LVDS Output Swing
V_O Single-ended, 100  differential 0.25
termination
HCSL Output Common ^V_OC
50 to ground
0.35
Mode
HCSL Output Swing
V_O
Single-ended
0.58
Duty Cycle
DC
All Output Formats
48
Typ
—
—
—
—
—
—
—
—
0.8
0.6
—
—
V_DD –
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
Max Units
—
V
0.15 x V_DD V
—
mA
—
mA
—
mA
—
mA
—
mA
—
mA
1.2
ns
0.9
ns
565
ps
800
ps
—
V
0.90
1.33
1.00
0.45
0.42
0.85
52
V_PPSE
V
V
V_PPSE
V
V_PPSE
%
6
Rev. 1.0