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SI512-13 Datasheet, PDF (7/20 Pages) Silicon Laboratories – Two selectable output frequencies | |||
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Si512/513
Table 4. Output Clock Jitter and Phase Noise (LVPECL)
VDD = 2.5 or 3.3 V ±10%, TA = â40 to +85 oC; Output Format = LVPECL
Parameter
Symbol
Test Condition
Min
Period Jitter JPRMS
10k samples1
â
(RMS)
Period Jitter JPPKPK
10k samples1
â
(Pk-Pk)
Phase Jitter
(RMS)
ÏJ
1.875 MHz to 20 MHz integration
â
bandwidth2 (brickwall)
12 kHz to 20 MHz integration band-
â
width (brickwall)2
Phase Noise,
ÏN
100 Hz
â
156.25 MHz
1 kHz
â
10 kHz
â
100 kHz
â
1 MHz
â
Additive RMS
JPSR
10 kHz sinusoidal noise
â
Jitter Due to
External Power
Supply Noise3
100 kHz sinusoidal noise
â
500 kHz sinusoidal noise
â
1 MHz sinusoidal noise
â
Spurious
SPR
LVPECL output, 156.25 MHz,
â
offset > 10 kHz
Typ
â
â
0.31
0.8
â86
â109
â116
â123
â136
3.0
3.5
3.5
3.5
â75
Max
Units
1.3
ps
11
ps
0.5
ps
1.0
ps
â
dBc/Hz
â
dBc/Hz
â
dBc/Hz
â
dBc/Hz
â
dBc/Hz
â
ps
â
ps
â
ps
â
ps
â
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5, 250 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 MHz.
3. 156.25 MHz. Increase in jitter on output clock due to sinewave noise added to VDD (2.5/3.3 V = 100 mVPP).
Rev. 1.0
7
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