SI5365 Datasheet, PDF (8/18 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5365
Table 3. Si5365 Pin Descriptions (Continued)
Pin # Pin Name I/O Signal Level
Description
3
RST
I LVCMOS External Reset.
Active low input that performs external hardware reset of device. Resets
all internal logic to a known state and forces the device registers to their
default value. Clock outputs are tristated during reset. After rising edge
of RST signal, the device will perform an internal self-calibration.
This pin has a weak pull-up.
4
FRQTBL I
3-Level Frequency Table Select.
This pin selects SONET/SDH, datacom, or SONET/SDH to datacom fre-
quency translation table.
L = SONET/SDH.
M = Datacom.
H = SONET/SDH to Datacom.
This pin has a weak pull-down.
5, 6, 15,
27, 32, 42,
62, 63, 76,
79, 81, 84,
86, 89, 91,
94, 96, 99,
100
7, 8, 14,
16, 18, 19,
26, 28, 31,
33, 36, 38,
41, 43, 46,
51, 56, 64,
65
V_DD
GND
V_DD
GND
Supply
Supply
V_DD.
The device operates from a 1.8 or 2.5 V supply. Bypass capacitors
should be associated with the following V_DD pins:
Pins
Bypass Cap
5, 6
0.1 µF
15
0.1 µF
27
0.1 µF
62, 63
76, 79
0.1 µF
1.0 µF
81, 84
86, 89
91, 94
0.1 µF
0.1 µF
0.1 µF
96, 99, 100 0.1 µF
Ground.
These pins must be connected to system ground. Minimize the ground
path impedance for optimal performance.
9
C1B
O LVCMOS CKIN1 Invalid Indicator.
This pin is an active high alarm output associated with CKIN1. Once trig-
gered, the alarm will remain high until CKIN1 is validated.
0 = No alarm on CKIN1.
1 = Alarm on CKIN1.
10
C2B
O LVCMOS CKIN2 Invalid Indicator.
This pin is an active high alarm output associated with CKIN2. Once trig-
gered, the alarm will remain high until CKIN2 is validated.
0 = No alarm on CKIN2.
1 = Alarm on CKIN2.
11
C3B
O LVCMOS CKIN3 Invalid Indicator.
This pin is an active high alarm output associated with CKIN3.
0 = No alarm on CKIN3.
1 = Alarm on CKIN3.
8
Preliminary Rev. 0.34