SI5365 Datasheet, PDF (10/18 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5365
Pin #
50
58
59
60
61
66
67
68
69
70
71
77
78
Table 3. Si5365 Pin Descriptions (Continued)
Pin Name I/O Signal Level
Description
DBL5
I
3-Level CKOUT5 Disable.
This pin performs the following functions:
L = Normal operation. Output path is active and signal format is deter-
mined by SFOUT inputs.
M = CMOS signal format. Overrides SFOUT signal format to allow
CKOUT5 to operate in CMOS format while the clock outputs operate in a
differential output format.
H = Powerdown. Entire CKOUT5 divider and output buffer path is pow-
ered down. CKOUT5 output will be in tristate mode during powerdown.
C1A
O LVCMOS CKIN1 Active Clock Indicator.
This pin serves as the CKIN1 active clock indicator.
0 = CKIN1 is not the active input clock.
1 = CKIN1 is currently the active input clock to the PLL.
C2A
O LVCMOS CKIN2 Active Clock Indicator.
This pin serves as the CKIN2 active clock indicator.
0 = CKIN2 is not the active input clock.
1 = CKIN2 is currently the active input clock to the PLL.
BWSEL0 I
BWSEL1
3-Level
Bandwidth Select.
These pins are three level inputs that select the DSPLL closed loop
bandwidth according to the Any-Rate Precision Clock Family Reference
Manual.
DIV34_0 I
DIV34_1
3-Level
CKOUT3 and CKOUT4 Divider Control.
These pins control the division of CKOUT3 and CKOUT4 relative to the
CKOUT2 output frequency. Detailed operations and timing characteris-
tics for these pins may be found in the Any-Rate Precision Clock Family
Reference Manual.
FRQSEL0 I
FRQSEL1
FRQSEL2
FRQSEL3
3-Level
Multiplier Select.
These pins are three level inputs that select the input clock and clock
multiplication setting according to the Any-Rate Precision Clock Family
Reference Manual, depending on the FRQTBL setting.
CKOUT3+ O
CKOUT3–
MULTI
Clock Output 3.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL settings. Output is differential for LVPECL, LVDS, and CML
compatible modes. For CMOS format, both output pins drive identical sin-
gle-ended clock outputs.
10
Preliminary Rev. 0.34