SI5365 Datasheet, PDF (5/18 Pages) Silicon Laboratories – PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Si5365
System
Power
Supply
VDD = 3.3 V
130 Ω
82 Ω
130 Ω
82 Ω
CKIN1+
CKIN1–
Ferrite
Bead
C10
1 µF
C1–9
0.1 µF
CKOUT1+
CKOUT1–
0.1 µF
+
100 Ω
–
0.1 µF
Input
Clock
Sources¹
VDD = 3.3 V
130 Ω
82 Ω
130 Ω
82 Ω
CKIN4+
CKIN4–
Clock
Outputs
Si5365
CKOUT5+
CKOUT5–
0.1 µF
+
100 Ω
–
0.1 µF
Manual/Automatic Clock
Selection (L)
Input Clock Select
Frequency Table Select
Frequency Select
Bandwidth Select
Signal Format Select
CKOUT_3 and CKOUT_4
Divider Control
Clock Output 2 Disable/
Bypass Mode Control
Clock Outputs 3 and 4
Disable
CKOUT5 Disable
Reset
AUTOSEL²
CKSEL[1:0]³
FRQTBL²
FRQSEL[3:0]²
BWSEL[1:0]²
SFOUT[1:0]²
DIV34[1:0]²
DBL2_BY²
DBL34
DBL5²
RST
ALRMOUT
CnB
Alarm Output Indicator
CKIN_n Invalid
Indicator (n = 1 to 3)
Notes: 1. Assumes differential LVPECL termination (3.3 V) on clock inputs.
2. Denotes tri-level input pins with states designated as L (ground), M (VDD/2), and H (VDD).
3. Assumes manual input clock selection.
Figure 2. Si5365 Typical Application Circuit
Preliminary Rev. 0.34
5