SI52144 Datasheet, PDF (8/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

Si52144
Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2.
Load Capacitance (each side)
Ce = 2 x CL – (Cs + Ci)
Total Capacitance (as seen by the crystal)
CLe
=
1
(
Ce1
+
1
Cs1
+
Ci1
+
1
)
Ce2 + Cs2 + Ci2
CL: Crystal load capacitance
CLe: Actual loading seen by crystal using standard value trim capacitors
Ce: External trim capacitors
Cs: Stray capacitance (terraced)
Ci: Internal capacitance (lead frame, bond wires, etc.)
2.2. OE Clarification
The OE pins are active high inputs used to enable and disable the output clocks. To enable the output clock, the OE
pin needs to be logic high and the I²C output enable bit needs to be logic high. There are two methods to disable
the output clocks: the OE is pulled to a logic low, or the I²C enable bit is set to a logic low. The OE pins is required
to be driven at all time and even though it has an internally 100 k resistor.
2.3. OE Assertion
The OE signals are active high input used for synchronous stopping and starting the DIFF output clocks respectively
while the rest of the clock generator continues to function. The assertion of the OE signal by making it logic high
causes stopped respective DIFF output to resume normal operation. No short or stretched clock pulses are produced
when the clock resumes. The maximum latency from the assertion to active outputs is no more than two to six output
clock cycles.
2.4. OE Deassertion
When the OE pin is deasserted by making its logic low, the corresponding DIFF output is stopped cleanly, and the
final output state is driven low.
2.5. SSON Clarification
SSON is an active input used to enable –0.5% spread on all DIFF outputs. When sampled high, –0.5% spread is
enabled on all DIFF outputs. When sampled low, the DIFF output frequencies are non-spread.
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Preliminary Rev. 0.1