SI52144 Datasheet, PDF (17/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

Pin #
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Name
VDD
DIFF2
DIFF2
DIFF3
DIFF3
VDD
OE3
SCLK
SDATA
VDD_CORE
XOUT
XIN/CLKIN
VSS_CORE
GND
Si52144
Table 7. Si52144 24-Pin QFN Descriptions
Type
PWR 3.3 V power supply
Description
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
PWR 3.3 V power supply
I,PU 3.3 V input to disable DIFF3 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I SMBus compatible SCLOCK
I/O SMBus compatible SDATA
PWR 3.3 V power supply
O 25.00 MHz crystal output, Float XOUT if using only CLKIN (clock input)
I 25.00 MHz crystal input or 3.3 V, 25 MHz clock Input
GND Ground
GND Ground for bottom pad of the IC
Preliminary Rev. 0.1
17