SI52144 Datasheet, PDF (19/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

Si52144
7. Package Outline
Figure 6 illustrates the package details for the Si52142. Table 8 lists the values for the dimensions shown in the
illustration.
Figure 6. 24-Pin Quad Flat No Lead (QFN) Package
Table 8. Package Diagram Dimensions
Symbol
A
A1
b
D
D2
e
E
E2
L
aaa
bbb
ccc
ddd
Millimeters
Min
Nom
Max
0.70
0.75
0.80
0.00
0.025
0.05
0.20
0.25
0.30
4.00 BSC
2.60
2.70
2.80
0.50 BSC
4.00 BSC
2.60
2.70
2.80
0.30
0.40
0.50
0.10
0.10
0.08
0.07
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VGGD-8.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020
specification for Small Body Components.
Preliminary Rev. 0.1
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