SI52144 Datasheet, PDF (16/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

Si52144
5. Pin Descriptions: 24-Pin QFN
Pin #
1,6
2
3
4
5
7
8
9
10
11
16
VDD 1
OE1¹ 2
SSON² ₃
VSS 4
OE2¹ 5
VDD 6
24 23 22 21 20 19
18 OE3¹
17 ^VDD
25
GND
16 _DIFF3
15 DIFF3
14 DIFF2
13 DIFF2
7 8 9 10 11 12
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Name
VDD
OE1
SSON
VSS
OE2
OE0
DIFF0
DIFF0
DIFF1
DIFF1
Table 7. Si52144 24-Pin QFN Descriptions
Type
PWR 3.3 V power supply
Description
I,PU 3.3 V input to disable DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PD 3.3 V input for Spread Control (internal 100 k pull-down).
Refer to Table 1 on page 4 for SSON specifications.
GND Ground
I,PU 3.3 V input to disable DIFF2 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I,PU 3.3 V input to disable DIFF0 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
O, DIF 0.7 V, 100 MHz differential clock
Preliminary Rev. 0.1