SI52144 Datasheet, PDF (5/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

Si52144
Table 2. AC Electrical Specifications
Parameter
Symbol
Condition
Crystal
Long-term Accuracy
Clock Input
CLKIN Duty Cycle
CLKIN Rise and Fall Times
L_ACC
T_DC
T_R/T_F
CLKIN Cycle to Cycle Jitter
CLKIN Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
DIFF Duty Cycle
Any DIFF Clock Skew from the
Earliest Bank to the Latest
Bank
T_CCJ
T_LTJ
V_IH
V_IL
I_IH
I_IL
T_DC
T_SKEW(win
dow)
Measured at V_DD/2 differential
Measured at V_DD/2
Measured between 0.2 V_DD and
0.8 V_DD
Measured at VDD/2
Measured at VDD/2
XIN/CLKIN pin
XIN/CLKIN pin
XIN/CLKIN pin, VIN = VDD
XIN/CLKIN pin, 0 < VIN <0.8
Measured at 0 V differential
Measured at 0 V differential
DIFF Cycle to Cycle Jitter
Output PCIe Gen1 REFCLK
Phase Jitter
T_CCJ
RMS_GEN1
Measured at 0 V differential
Includes PLL BW 1.5–22 MHz,
ζ = 0.54, Td=10 ns,
Ftrk=1.5 MHz with BER = 1E-12
Output PCIe Gen2 REFCLK
Phase Jitter
RMS_GEN2 Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54,
Td=12 ns), Low Band, F < 1.5 MHz
Output PCIe Gen2 REFCLK
Phase Jitter
RMS_GEN2
Includes PLL BW 8–16 MHz, Jitter
Peaking = 3 dB, ζ = 0.54,
Td=12 ns), High Band,
1.5 MHz < F < Nyquist
Output Phase Jitter Impact— RMS_GEN3
PCIe Gen3
Includes PLL BW 2–4 MHz,
CDR = 10 MHz)
DIFF Long Term Accuracy
DIFF Rising/Falling Slew Rate
L_ACC
T_R/T_F
Measured at 0 V differential
Measured differentially from
±150 mV
Voltage High
Voltage Low
Crossing Point Voltage at
0.7 V Swing
V_HIGH
V_LOW
V_OX
Enable/Disable and Setup
Clock Stabilization from
Power-up
T_STABLE
Stopclock Set-up Time
T_SS
Min
—
47
0.5
—
—
2
—
—
–35
45
—
—
0
0
0
0
—
1
—
–0.3
300
—
10.0
Typ Max Unit
—
250 ppm
—
53
%
—
4.0 V/ns
—
250
ps
—
350
ps
— VDD+0.3 V
—
0.8
V
—
35
uA
—
—
uA
—
55
%
—
50
ps
35
50
ps
40
108
ps
2
3.0
ps
2
3.1
ps
0.5
1.0
ps
—
100 ppm
—
8
V/ns
—
1.15
V
—
—
V
—
550 mV
—
1.8
ms
—
—
ns
Preliminary Rev. 0.1
5