SI52144 Datasheet, PDF (1/20 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD OUTPUT GENERATOR

Si52144
PCI-EXPRESS GEN 1, GEN 2, & GEN 3 CLOCK QUAD
OUTPUT GENERATOR
Features
 PCI-Express Gen 1, Gen 2, &  25 MHz crystal input or clock
Gen 3 Compliant
input
 Low power push-pull type
differential output buffers
 I²C support with readback
capabilities
 Integrated resistors on differential _{ Triangular spread spectrum}
clocks
profile for maximum
 Dedicated output enable
electromagnetic interference
hardware pin for each clock
(EMI) reduction
 Hardware selectable spread
control
 Four PCI-Express Clocks
 Industrial temperature:
–40 to 85 ^oC
 3.3 V power supply
 24-pin QFN package
Ordering Information:
See page 18
Applications
 Network attached storage
 Multi-function printer
 Wireless access point
 Routers
Description
The Si52144 is a spread-controlled PCIe clock generator that can source
four PCIe clocks simultaneously. The device has four hardware output
enable control inputs for enabling the respective differential outputs on the
fly while powered on along with the spread control hardware pin to enable
spread for EMI reduction. In addition to the hardware control pins, I²C
programmability is also available to promptly achieve optimum clock
signal integrity through skew and edge rate control on true, compliment,
or both differential outputs as well as amplitude control.
Functional Block Diagram
Pin Assignments
VDD 1
OE1¹ 2
SSON² 3
VSS 4
OE2¹ 5
VDD 6
24 23 22 21 20 19
18 OE3¹
17 VDD
25
GND
16 DIFF3
15 DIFF3
14 DIFF2
13 DIFF2
7 8 9 10 11 12
Notes:
1. Internal 100 kohm pull-up.
2. Internal 100 kohm pull-down.
Patents pending
XIN/CLKIN
XOUT
PLL
(SSC)
Divider
SCLK
SDATA
OE [3:0]
SSON
Control & Memory
Control RAM
DIFF0
DIFF1
DIFF2
DIFF3
Preliminary Rev. 0.1 12/11
Copyright © 2011 by Silicon Laboratories
Si52144
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.