SI823X Datasheet, PDF (7/52 Pages) Silicon Laboratories – 0.5 AND 4.0 AMP ISODRIVERS (2.5 AND 5 KVRMS)

Si823x
Table 1. Electrical Characteristics¹ (Continued)
4.5 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V. TA = –40 to +125 °C. Typical specs at 25 °C
Parameter
Symbol
Test Conditions
Min
Typ Max Units
VDDI Undervoltage Threshold ^VDDI_UV+
VDDI rising
3.60
VDDI Undervoltage Threshold ^VDDI_UV–
VDDI falling
3.30
VDDI Lockout Hysteresis
VDDI_HYS
—
VDDA, VDDB Undervoltage
Threshold
VDDA_UV+,
VDDB_UV+
VDDA, VDDB rising
5 V threshold
See Figure 36 on page 25.
5.20
8 V threshold
See Figure 37 on page 25.
7.50
10 V threshold
See Figure 38 on page 25.
9.60
12.5 V threshold
See Figure 39 on page 25.
12.4
VDDA, VDDB Undervoltage
Threshold
VDDA_UV–,
VDDB_UV–
VDDA, VDDB falling
5 V threshold
See Figure 36 on page 25.
4.90
8 V threshold
See Figure 37 on page 25.
7.20
10 V threshold
See Figure 38 on page 25.
9.40
12.5 V threshold
See Figure 39 on page 25.
11.6
VDDA, VDDB
Lockout hysteresis
VDDA, VDDB
Lockout hysteresis
VDDA, VDDB
Lockout hysteresis
VDDA_HYS,
VDDB_HYS
UVLO voltage = 5 V
—
VDDA_HYS,
VDDB_HYS
UVLO voltage = 8 V
—
VDDA_HYS,
VDDB_HYS
UVLO voltage = 10 V or 12.5 V
—
AC Specifications
4.0 4.45 V
3.70 4.15 V
250 — mV
5.80 6.30 V
8.60 9.40 V
11.1 12.2 V
13.8 14.8 V
5.52 6.0
V
8.10 8.70 V
10.1 10.9 V
12.8 13.8 V
280 — mV
600 — mV
1000 — mV
Minimum Pulse Width
—
10
—
ns
Propagation Delay
Pulse Width Distortion
|t_PLH - t_PHL|
Minimum Overlap Time²
t_PHL, t_PLH
PWD
TDD
CL = 200 pF
DT = VDDI, No-Connect
—
30
60
ns
—
— 5.60 ns
—
0.4
—
ns
Programmed Dead Time³
Figure 41, RDT = 100 k
—
900 —
ns
DT
Figure 41, RDT = 6 k
—
70
—
ns
Output Rise and Fall Time
C_L = 200 pF (Si8230/1/2)
—
—
12
ns
t_R,t_F
C_L = 200 pF (Si8233/4/5/6)
—
—
20
ns
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 k.
Rev. 0.3
7