SI53119 Datasheet, PDF (7/35 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53119
Table 5. Output Skew, PLL Bandwidth and Peaking
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
CLK_IN, DIF[x:0]
DIF[11:0]
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Test Condition
Input-to-Output Delay in PLL Mode
Nominal Value^1,2,3,4
Input-to-Output Delay in Bypass Mode
Nominal Value^2,4,5
Input-to-Output Delay Variation in PLL mode
Over Voltage and Temperature^2,4,5
Input-to-Output Delay Variation in Bypass Mode
Over Voltage and Temperature^2,4,5
Output-to-Output Skew across all 19 Outputs
(Common to Bypass and PLL Mode)^1,2,3,4,5
(HBW_BYPASS_LBW = 0)⁶
(HBW_BYPASS_LBW = 1)⁶
(HBW_BYPASS_LBW = 0)⁷
(HBW_BYPASS_LBW = 1)⁷
Min
–100
2.5
–50
–250
0
—
—
—
—
TYP
18
3.6
20
20
0.4
0.1
0.7
2
Max Unit
100
ps
4.5
ns
50
ps
250
ps
50
ps
2.0
dB
2.5
dB
1.4 MHz
4
MHz
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. This parameter is deterministic for a given device.
4. Measured with scope averaging on to find mean value.
5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7. Measured at 3 db down or half power point.
Rev. 1.1
7