SI53119 Datasheet, PDF (1/35 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53119
19-OUTPUT PCIE GEN 3 BUFFER
Features
 Nineteen 0.7 V low-power, push-  PLL or bypass mode
pull HCSL PCIe Gen 3 outputs _{ Spread spectrum tolerable}
 100 MHz /133 MHz PLL
 1.05 to 3.3 V I/O supply voltage

operation, supports PCIe and
QPI

PLL bandwidth SW SMBUS
programming overrides the latch


value from HW pin
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
compliant)


9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single


Gen 3 SRNS Compliant
100 ps input-to-output delay
control network 3.3 V supply ^{ Extended Temperature:}
voltage operation
–40 to 85 °C
 Separate VDDIO for outputs
 72-pin QFN
 For variations of this device,
contact Silicon Labs
Ordering Information:
See page 31.
Pin Assignments
Applications
 Server
 Storage
 Data center
 Enterprise switches and routers
Description
The Si53119 is a 19-output, low-power HCSL differential clock buffer that
meets all of the performance requirements of the Intel DB1200ZL
specification. The device is optimized for distributing refere nce clocks for
Intel^® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/
Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output can be enabled through I²C
for maximum flexibility and power savings. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it
for free at www.silabs.com/pcie-learningcenter.
VDDA 1
GNDA 2
100M_133M 3
HBW_BYPASS_LBW 4
PWRGD / PWRDN 5
GND 6
VDDR 7
CLK_IN 8
CLK_IN 9
SA_0 10
SDA 11
SCL 12
SA_1 13
FBOUT_NC 14
FBOUT_NC 15
GND 16
DIF_0 17
DIF_0 18
Si53119
Patents pending
54 DIF_12
53 DIF_12
52 VDD_IO
51 GND
50 DIF_11
49 DIF_11
48 DIF_10
47 DIF_10
46 GND
45 ^VDD
44 DIF_9
43 DIF_9
42 DIF_8
41 DIF_8
40 VDD_IO
39 GND
38 DIF_7
37 DIF_7
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53119