SI53119 Datasheet, PDF (6/35 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53119
Table 4. Clock Input Parameters
T_A = 0–70 °C; supply voltage V_DD = 3.3 V ±5%
Parameter
Input High Voltage
Symbol
V_IHDIF
Input Low Voltage
V_IHDIF
Input Common Mode
Voltage
Input Amplitude, CLK_IN
Input Slew Rate, CLK_IN
Input Duty Cycle
V_com
V_swing
dv/dt
Input Jitter–Cycle to Cycle
Input Frequency
J_DFin
F_ibyp
F_iPLL
FiPLL
Input SS Modulation Rate fMODIN
Test Condition
Differential Inputs
(singled-ended measurement)
Differential Inputs
(singled-ended measurement)
Common mode input voltage
Peak to Peak Value
Measured differentially
Measurement from differential wave
form
Differential measurement
VDD = 3.3 V, bypass mode
VDD = 3.3 V, 100 MHz PLL Mode
VDD = 3.3 V, 133.33 MHz PLL Mode
Triangle wave modulation
Min Typ Max
600 700 1150
Vss-
0
300
300
300
1000
300
1450
0.4
8
45
50
55
125
33
150
90 100 110
120 133.33 147
30 31.5 33
Unit
mV
mV
mV
mV
V/ns
%
ps
MHz
MHz
MHz
kHz
6
Rev. 1.1