SI53119 Datasheet, PDF (32/35 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53119
8. Package Outline
Figure 12 illustrates the package details for the Si53119. Table 26 lists the values for the dimensions shown in the
illustration.
Figure 12. 72-Pin Quad Flat No Lead (QFN) Package
Table 26. Package Dimensions
Dimension
Min
A
0.80
Nom
Max
0.85
0.90
Dimension
Min
Nom
Max
E2
5.90
6.00
6.10
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
L
0.30
0.40
0.50
aaa
0.10
D
10.00 BSC.
bbb
0.10
D2
5.90
6.00
6.10
ccc
0.08
e
0.50 BSC.
ddd
0.10
E
10.00 BSC.
eee
0.05
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 1.1