SI53119 Datasheet, PDF (21/35 Pages) Silicon Laboratories – 19-OUTPUT PCIE GEN 3 BUFFER

Si53119
4.3. Control Registers
Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
Output(s)
Affected
0
100M_133M#
Frequency Select
133 MHz
100 MHz
R
Latched at
DIF[11:0]
power up
1
Reserved
0
2
Reserved
0
3
Output Enable DIF 16
Low/Low
Enable
RW
1
DIF_16
4
Output Enable DIF 17
Low/Low
Enable
RW
1
DIF_17
5
Output Enable DIF 18
Low/Low
Enable
RW
1
DIF_18
6
PLL Mode 0
See PLL Operating Mode
Readback Table
R
Latched at
power up
7
PLL Mode 1
See PLL Operating Mode
Readback Table
R
Latched at
power up
Table 18. Byte 1: Output Enable Control Register
Bit
Description
If Bit = 0 If Bit = 1
Type
Default Output(s)
Affected
0
Output Enable DIF 0
Low/Low
Enabled
RW
1
DIF[0]
1
Output Enable DIF 1
Low/Low
Enabled
RW
1
DIF[1]
2
Output Enable DIF 2
Low/Low
Enabled
RW
1
DIF[2]
3
Output Enable DIF 3
Low/Low
Enabled
RW
1
DIF[3]
4
Output Enable DIF 4
Low/Low
Enabled
RW
1
DIF[4]
5
Output Enable DIF 5
Low/Low
Enabled
RW
1
DIF[5]
6
Output Enable DIF 6
Low/Low
Enabled
RW
1
DIF[6]
7
Output Enable DIF 7
Low/Low
Enabled
RW
1
DIF[7]
Rev. 1.1
21