SI4430-B1 Datasheet, PDF (66/74 Pages) Silicon Laboratories – Si4430/31/32 ISM TRANSCEIVER

Si4430/31/32-B1
13. Pin Descriptions: Si4430/31/32
VDD_RF 1
TX 2
RXp 3
RXn 4
NC 5
6
20 19 18 17 ₁₆
15 SCLK
GND
PAD
14 SDI
13 SDO
12 VDD_DIG
7 8 9 10 ^{11 NC}
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PKG
Pin Name
VDD_RF
TX
RXp
RXn
NC
ANT
GPIO_0
GPIO_1
GPIO_2
VR_DIG
NC
VDD_DIG
SDO
SDI
SCLK
nSEL
nIRQ
XOUT
XIN
SDN
PADDLE_GND
I/O
VDD
O
I
I
—
O
I/O
I/O
I/O
O
—
VDD
O
I
I
I
O
O
I
I
GND
Description
+1.8 to +3.6 V supply voltage input to all analog +1.7 V regulators. The recommended V_DD supply voltage
is +3.3 V.
Transmit output pin. The PA output is an open-drain connection so the L-C match must supply VDD
(+3.3 VDC nominal) to this pin.
Differential RF input pins of the LNA. See application schematic for example matching network.
No Connect. Not connected internally to any circuitry.
Extra antenna or TR switch control to be used if more GPIO are required. Pin is a hardwired version of
GPIO setting 11000, Antenna 2 and can be manually controlled by the antdiv[2:0] bits in register 08h. See
register description of 08h.
General Purpose Digital I/O that may be configured through the registers to perform various functions
including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW,
AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for
more information.
Regulated Output Voltage of the Digital 1.7 V Regulator. A 1 µF decoupling capacitor is required.
Internally this pin is tied to the paddle of the package. This pin should be left unconnected or connected to
GND only.
+1.8 to +3.6 V supply voltage input to the Digital +1.7 V Regulator. The recommended V_DD supply voltage
is +3.3 V.
0–V_DD V digital output that provides a serial readback function of the internal control registers.
Serial Data input. 0–V_DD V digital input. This pin provides the serial data stream for the 4-line serial data
bus.
Serial Clock input. 0–V_DD V digital input. This pin provides the serial data clock function for the 4-line
serial data bus. Data is clocked into the Si4430/31/32 on positive edge transitions.
Serial Interface Select input. 0– V_DD V digital input. This pin provides the Select/Enable function for the 4-
line serial data bus. The signal is also used to signify burst read/write mode.
General Microcontroller Interrupt Status output. When the Si4430/31/32 exhibits anyone of the Interrupt
Events the nIRQ pin will be set low=0. Please see the Control Logic registers section for more information
on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a cor-
responding SPI Interrupt Status Registers, Address 03h and 04h. No external resistor pull-up is required,
but it may be desirable if multiple interrupt lines are connected.
Crystal Oscillator Output. Connect to an external 30 MHz crystal or to an external source. If using an
external source with no crystal then dc coupling with a nominal 0.8 VDC level is recommended with a
minimum amplitude of 700 mVpp.
Crystal Oscillator Input. Connect to an external 30 MHz crystal or leave floating when driving with an
external source on XOUT..
Shutdown input pin. 0–V_DD V digital input. SDN should be = 0 in all modes except Shutdown mode. When
SDN =1 the chip will be completely shutdown and the contents of the registers will be lost.
The exposed metal paddle on the bottom of the Si4430/31/32 supplies the RF and circuit ground(s) for the
entire chip. It is very important that a good solder connection is made between this exposed metal paddle
and the ground plane of the PCB underlying the Si4430/31/32.
66
Rev 1.1