SI4430-B1 Datasheet, PDF (19/74 Pages) Silicon Laboratories – Si4430/31/32 ISM TRANSCEIVER

Si4430/31/32-B1
SDI
SCLK
SDO
First Bit
Last Bit
RW
=0
A6
A5
A4
A3
A2
A1
A0
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
First Bit
Last Bit
D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 4. SPI Timing—READ Mode
The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers without
having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI
interface will automatically increment the ADDR and read from/write to the next address. An example burst write
transaction is illustrated in Figure 5 and a burst read in Figure 6. As long as nSEL is held low, input data will be
latched into the Si4430/31/32 every eight SCLK cycles.
SDI
SCLK
First Bit
Last Bit
RW
=1
A6
A5
A4
A3
A2
A1
A0
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
nSEL
Figure 5. SPI Timing—Burst Write Mode
First Bit
Last Bit
SDI
RW
=0
A6
A5
A4
A3
A2
A1
A0
D7
=X
D6
=X
D5
=X
D4
=X
D3
=X
D2
=X
D1
=X
D0
=X
SCLK
SDO
First Bit
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 6. SPI Timing—Burst Read Mode
Rev 1.1
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