SI4430-B1 Datasheet, PDF (65/74 Pages) Silicon Laboratories – Si4430/31/32 ISM TRANSCEIVER

Si4430/31/32-B1
Table 18. Register Descriptions (Continued)
Add R/W
Function/Desc
Data
D7
D6
D5
D4
D3
D2
D1
31 R
EzMAC status
0
rxcrc1
pksrch
pkrx
pkvalid
crcerror
pktx
32 R/W
Header Control 1
bcen[3:0]
hdch[3:0]
33 R/W
Header Control 2
skipsyn
hdlen[2]
hdlen[1]
hdlen[0]
fixpklen synclen[1] synclen[0]
34 R/W
Preamble Length
prealen[7]
prealen[6] prealen[5] prealen[4] prealen[3] prealen[2] prealen[1]
35 R/W Preamble Detection Control
preath[4]
preath[3]
preath[2]
preath[1] preath[0] rssi_off[2] rssi_off[1]
36 R/W
Sync Word 3
sync[31]
sync[30]
sync[29]
sync[28]
sync[27] sync[26] sync[25]
37 R/W
Sync Word 2
sync[23]
sync[22]
sync[21]
sync[20]
sync[19] sync[18] sync[17]
38 R/W
Sync Word 1
sync[15]
sync[14]
sync[13]
sync[12]
sync[11] sync[10]
sync[9]
39 R/W
Sync Word 0
sync[7]
sync[6]
sync[5]
sync[4]
sync[3]
sync[2]
sync[1]
3A R/W
Transmit Header 3
txhd[31]
txhd[30]
txhd[29]
txhd[28]
txhd[27]
txhd[26]
txhd[25]
3B R/W
Transmit Header 2
txhd[23]
txhd[22]
txhd[21]
txhd[20]
txhd[19]
txhd[18]
txhd[17]
3C R/W
Transmit Header 1
txhd[15]
txhd[14]
txhd[13]
txhd[12]
txhd[11]
txhd[10]
txhd[9]
3D R/W
Transmit Header 0
txhd[7]
txhd[6]
txhd[5]
txhd[4]
txhd[3]
txhd[2]
txhd[1]
3E R/W
Transmit Packet Length
pklen[7]
pklen[6]
pklen[5]
pklen[4]
pklen[3]
pklen[2]
pklen[1]
3F R/W
Check Header 3
chhd[31]
chhd[30]
chhd[29]
chhd[28]
chhd[27] chhd[26] chhd[25]
40 R/W
Check Header 2
chhd[23]
chhd[22]
chhd[21]
chhd[20]
chhd[19] chhd[18] chhd[17]
41 R/W
Check Header 1
chhd[15]
chhd[14]
chhd[13]
chhd[12]
chhd[11] chhd[10]
chhd[9]
42 R/W
Check Header 0
chhd[7]
chhd[6]
chhd[5]
chhd[4]
chhd[3]
chhd[2]
chhd[1]
43 R/W
Header Enable 3
hden[31]
hden[30]
hden[29]
hden[28]
hden[27] hden[26]
hden[25]
44 R/W
Header Enable 2
hden[23]
hden[22]
hden[21]
hden[20]
hden[19] hden[18]
hden[17]
45 R/W
Header Enable 1
hden[15]
hden[14]
hden[13]
hden[12]
hden[11] hden[10]
hden[9]
46 R/W
Header Enable 0
hden[7]
hden[6]
hden[5]
hden[4]
hden[3]
hden[2]
hden[1]
47 R
Received Header 3
rxhd[31]
rxhd[30]
rxhd[29]
rxhd[28]
rxhd[27]
rxhd[26]
rxhd[25]
48 R
Received Header 2
rxhd[23]
rxhd[22]
rxhd[21]
rxhd[20]
rxhd[19]
rxhd[18]
rxhd[17]
49 R
Received Header 1
rxhd[15]
rxhd[14]
rxhd[13]
rxhd[12]
rxhd[11]
rxhd[10]
rxhd[9]
4A R
Received Header 0
rxhd[7]
rxhd[6]
rxhd[5]
rxhd[4]
rxhd[3]
rxhd[2]
rxhd[1]
4B R
Received Packet Length
rxplen[7]
rxplen[6]
rxplen[5]
rxplen[4]
rxplen[3] rxplen[2] rxplen[1]
4C-4E
Reserved
4F R/W
ADC8 Control
Reserved
Reserved
adc8[5]
adc8[4]
adc8[3]
adc8[2]
adc8[1]
50-5F
Reserved
60 R/W
Channel Filter Coefficient
Address
Inv_pre_th[3] Inv_pre_th[2] Inv_pre_th[1] Inv_pre_th[0] chfiladd[3] chfiladd[2] chfiladd[1]
61
Reserved
62 R/W Crystal Oscillator/Control Test
pwst[2]
pwst[1]
pwst[0]
clkhyst
enbias2x enamp2x
bufovr
63-68
Reserved
69 R/W
AGC Override 1
Reserved
sgi
agcen
lnagain
pga3
pga2
pga1
6A-6C
Reserved
6D R/W
TX Power
Reserved
Reserved Reserved Reserved
Ina_sw
txpow[2]
txpow[1]
6E R/W
TX Data Rate 1
txdr[15]
txdr[14]
txdr[13]
txdr[12]
txdr[11]
txdr[10]
txdr[9]
6F R/W
TX Data Rate 0
txdr[7]
txdr[6]
txdr[5]
txdr[4]
txdr[3]
txdr[2]
txdr[1]
70 R/W Modulation Mode Control 1
Reserved
Reserved txdtrtscale enphpwdn manppol enmaninv enmanch
71 R/W Modulation Mode Control 2
trclk[1]
trclk[0]
dtmod[1]
dtmod[0]
eninv
fd[8]
modtyp[1]
72 R/W
Frequency Deviation
fd[7]
fd[6]
fd[5]
fd[4]
fd[3]
fd[2]
fd[1]
73 R/W
Frequency Offset 1
fo[7]
fo[6]
fo[5]
fo[4]
fo[3]
fo[2]
fo[1]
74 R/W
Frequency Offset 2
Reserved
Reserved Reserved Reserved Reserved Reserved
fo[9]
75 R/W
Frequency Band Select
Reserved
sbsel
hbsel
fb[4]
fb[3]
fb[2]
fb[1]
76 R/W Nominal Carrier Frequency 1
fc[15]
fc[14]
fc[13]
fc[12]
fc[11]
fc[10]
fc[9]
77 R/W Nominal Carrier Frequency 0
fc[7]
fc[6]
fc[5]
fc[4]
fc[3]
fc[2]
fc[1]
78
Reserved
79 R/W Frequency Hopping Channel
Select
fhch[7]
fhch[6]
fhch[5]
fhch[4]
fhch[3]
fhch[2]
fhch[1]
7A R/W Frequency Hopping Step Size
fhs[7]
fhs[6]
fhs[5]
fhs[4]
fhs[3]
fhs[2]
fhs[1]
7B
Reserved
7C R/W
TX FIFO Control 1
Reserved
Reserved
txafthr[5]
txafthr[4]
txafthr[3] txafthr[2] txafthr[1]
7D R/W
TX FIFO Control 2
Reserved
Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1]
7E R/W
RX FIFO Control
Reserved
Reserved
rxafthr[5]
rxafthr[4]
rxafthr[3] rxafthr[2] rxafthr[1]
7F R/W
FIFO Access
fifod[7]
fifod[6]
fifod[5]
fifod[4]
fifod[3]
fifod[2]
fifod[1]
Note: Detailed register descriptions are available in “AN440: EZRadioPRO Detailed Register Descriptions.”
D0
pksent
prealen[8]
prealen[0]
rssi_off[0]
sync[24]
sync[16]
sync[8]
sync[0]
txhd[24]
txhd[16]
txhd[8]
txhd[0]
pklen[0]
chhd[24]
chhd[16]
chhd[8]
chhd[0]
hden[24]
hden[16]
hden[8]
hden[0]
rxhd[24]
rxhd[16]
rxhd[8]
rxhd[0]
rxplen[0]
POR
Default
—
0Ch
22h
08h
2Ah
2Dh
D4h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
—
—
—
—
—
adc8[0]
10h
chfiladd[0] 00h
enbuf
24h
pga0
20h
txpow[0]
18h
txdr[8]
0Ah
txdr[0]
3Dh
enwhite
0Ch
modtyp[0] 00h
fd[0]
20h
fo[0]
00h
fo[8]
00h
fb[0]
75h
fc[8]
BBh
fc[0]
80h
fhch[0]
00h
fhs[0]
00h
txafthr[0]
37h
txaethr[0] 04h
rxafthr[0]
37h
fifod[0]
—
Rev 1.1
65