SI5321 Datasheet, PDF (6/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
Table 2. DC Characteristics, V_DD = 3.3 V
(V_DD33 = 3.3 V ±5%, T_A = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max Unit
Supply Current 1
I_DD
622.08 MHz In,
—
141
155
mA
19.44 MHz Out
Supply Current 2
I_DD
19.44 MHz In,
—
135
145
mA
622.08 MHz Out
Power Dissipation Using 3.3 V Supply
Clock Output
Common Mode Input Voltage^1,2,3
(CLKIN)
Single-Ended Input Voltage^2,3,4
(CLKIN)
Differential Input Voltage Swing^2,3,4
(CLKIN)
P_D
V_ICM
V_IS
V_ID
19.44 MHz In,
622.08 MHz Out
See Figure 1A
See Figure 1B
—
445
479
mW
1.0
1.5
2.0
V
200
—
500⁴ mV_PP
200
—
500⁴ mV_PP
Input Impedance
R_IN
(CLKIN+, CLKIN–)
—
80
—
k
Differential Output Voltage Swing
(CLKOUT)
V_OD
100  Load
750
825 1100 mV_PP
Line-to-Line,
FRQSEL[0:2] = 011
Output Common Mode Voltage
(CLKOUT)
V_OCM
100  Load
Line-to-Line
1.4
1.8
2.2
V
Output Short to GND (CLKOUT)
I_SC(–)
–60
—
—
mA
Output Short to V_DD25 (CLKOUT)
I_SC(+)
—
15
—
mA
Input Voltage Low (LVTTL Inputs)
V_IL
—
—
0.8
V
Input Voltage High (LVTTL Inputs)
V_IH
2.0
—
—
V
Input Low Current (LVTTL Inputs)
I_IL
—
—
50
A
Input High Current (LVTTL Inputs)
I_IH
—
—
50
A
Internal Pulldowns (LVTTL Inputs)
I_pd
Input Impedance (LVTTL Inputs)
R_IN
—
—
50
A
50
—
—
k
Output Voltage Low (LVTTL Outputs)
V_OL
I_O = 0.5 mA
—
—
0.4
V
Output Voltage High (LVTTL Outputs) V_OH
I_O = 0.5 mA
2.0
—
—
V
Notes:
1. The Si5321 device provides weak 1.5 V internal biasing that enables ac-coupled operation.
2. Clock inputs may be driven differentially or single-endedly. When driven single-endedly, the unused input should be ac-
coupled to ground.
3. Transmission line termination, when required, must be provided externally.
4. Although the Si5321 device can operate with input clock swings as high as 1500 mV_PP, Silicon Laboratories recommends
maintaining the input clock amplitude below 500 mV_PP for optimal performance.
6
Rev. 2.5