SI5321 Datasheet, PDF (20/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
Once the LOS alarm is asserted, it is held high until the
input clock is validated over a time period designated by
the VALTIME pin. When VALTIME is low, the validation
time period is about 1 ms. When VALTIME is high, the
validation time period is about 100 ms. If another LOS
condition is detected on the input clock during the
validation time (i.e., if another set of 1111 or 0000
samples are detected), the LOS alarm remains asserted
and the validation time starts over. When the LOS alarm
is finally released, the Si5321 exits digital hold mode
and locks to the input clock. The LOS alarm is
automatically set high at power-on and at every low-to-
high transition of the RSTN/CAL pin. In these cases, the
Si5321 undergoes a self-calibration before releasing the
LOS alarm and locking to the input clock.
The Si5321 also provides an output indicating the digital
hold status of the device, DH_ACTV. The Si5321 only
enters the digital hold mode upon the loss of the input
clock. When this occurs, the LOS alarm will also be
active. Therefore, applications that require monitoring of
the status of the Si5321 need only monitor the
CAL_ACTV and either the LOS or DH_ACTV outputs to
know the state of the device.
2.5. Digital Hold of the PLL
When no valid input clock is available, the Si5321
digitally holds the internal oscillator to its last frequency
value. This provides a stable clock to the system until an
input clock is valid again. This clock maintains stable
operation in the presence of constant voltage and
temperature. The frequency accuracy specifications for
digital hold mode are given in Table 4 on page 10.
2.6. Hitless Recovery from Digital Hold
When the Si5321 device is locked to a valid input clock,
a loss of the input clock switches the device to digital
hold mode. When the input clock signal returns, the
device performs a hitless transition from digital hold
mode back to the selected input clock. That is, the
device executes “phase build-out” to absorb the phase
difference between the internal VCO clock operating in
digital hold mode and the new/returned input clock. The
maximum phase step seen at the clock output during
this transition, and the maximum slope of this step, is
specified in Table 4 on page 10.
Asserting the Fixed Delay (FXDDELAY) pin disables
this feature and the output clock phase and frequency
locks with a known phase relationship to the input clock.
Consequently, abrupt phase change on the input clock
propagates through the device and the output slews at
the loop bandwidth until the phase relationship is
restored.
m_PT
t_{PT_MTIE}
Recovery from digital hold
Figure 8. Recovery from Digital Hold
2.7. Reset
The Si5321 provides a Reset/Calibration pin (RSTN/
CAL) that resets the device and disables all of the
device outputs. When the RSTN/CAL pin is driven low,
the internal circuitry enters reset mode and all LVTTL
outputs are forced into a high-impedance state. Also,
the CLKOUT+ and CLKOUT– pins are connected to
V_DD25 through 100  on-chip resistors. This feature is
useful for applications that employ redundant clock
sources and for in-circuit test applications. A low-to-high
transition on RSTN/CAL initializes all digital logic to a
known condition and initiates self-calibration of the
DSPLL. At the completion of self-calibration, the DSPLL
begins to lock to the clock input signal.
2.8. PLL Self-Calibration
The Si5321 achieves optimal jitter performance by
using self-calibration circuitry to set the VCO center
frequency and loop gain parameters within the DSPLL.
Internal circuitry generates self calibration automatically
on powerup or after a loss-of-power condition. Self-
calibration also can be manually initiated by a low-to-
high transition on the RSTN/CAL input.
A self-calibration should be initiated after changing the
state of the FEC[2:0] inputs. Whether manually initiated
or automatically initiated at powerup, the self-calibration
process requires the presence of a valid input clock.
If the self-calibration is initiated without a valid input
clock, the device waits for a valid input clock before
executing the self-calibration. The Si5321 does not
provide an output clock while waiting for a valid input
clock or while executing its self-calibration. When the
input clock is validated, the calibration procedure
executes to completion; the device locks to the input
clock, and the output clock turns on. Subsequent losses
of the input clock do not require self-calibration. If the
input clock is lost following self-calibration, the device
enters digital hold mode with the output clock frequency
held to its last value before the LOS condition was
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Rev. 2.5