SI5321 Datasheet, PDF (17/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC

Si5321
2. Functional Description
The Si5321 is a high-performance precision clock
multiplication and clock generation device. This device
accepts a clock input in the 19, 39, 78, 155, 311, or
622 MHz range, attenuates significant amounts of jitter,
and multiplies the input clock frequency to generate a
clock output in the 19, 39, 78, 155, 311, 622, 1250, or
2500 MHz range. Additional forward or reverse clock
rate scaling by a factor of 255/238, 255/237, or 66/64 is
provided. This allows systems to easily provide clocks
that are scaled for forward error correction (FEC) rates.
The 255/238 and 255/237 factors support the ITU-T
G.709 requirements for optical transport unit (OTU) OC-
48 and OC-192 rates. The 66/64 factor allows
conversion between XSBI and 10 GbE Base R rates.
Typical applications for the Si5321 in SONET/SDH
systems are generation and/or cleaning of 19.44, 38.88,
77.76, 155.52, 311.04, 622.08, 1244.16, or
2488.32 MHz clocks from 19.44, 38.88, 77.76, 155.52,
311.04, or 622.08 MHz clock sources.
The Si5321 employs Silicon Laboratories DSPLL^®
technology to provide excellent jitter performance while
minimizing the external component count and
maximizing flexibility and ease of use. The Si5321
DSPLL phase locks to the input clock signal, attenuates
jitter, and multiplies the clock frequency to generate the
device’s SONET/SDH-compliant clock output. The
DSPLL loop bandwidth is user selectable, allowing
Si5321 jitter performance optimization for different
applications. The Si5321 can produce a clock output
with jitter generation as low as 0.3 ps_RMS (see Table 4
on page 10), making the device an ideal solution for
clock multiplication in SONET/SDH (including OC-48,
OC-192, and OC768), Gigabit Ethernet, and 10 GbE
systems.
The Si5321 monitors the clock input signal for loss-of-
signal and provides a loss-of-signal (LOS) alarm when it
detects missing pulses. The Si5321 provides a digital
hold capability that allows the device to continue
generation of a stable output clock when the input
reference is lost.
2.1. DSPLL^®
The Si5321’s phase-locked loop (PLL) uses Silicon
Laboratories' DSPLL technology to eliminate jitter,
noise, and the need for external loop filter components
found in traditional PLL implementations. This is
achieved by using a digital signal processing (DSP)
algorithm to replace the loop filter commonly found in
analog PLL designs. This algorithm processes the
phase detector error term and generates a digital
control value to adjust the frequency of the voltage-
controlled oscillator (VCO). The technology produces
low phase noise clocks with less jitter than is generated
using traditional methods. See Figure 4 for an example
phase noise plot. In addition, because external loop
filter components are not required, sensitive noise entry
points are eliminated thus making the DSPLL less
susceptible to board-level noise sources. This digital
technology also provides highly-stable and consistent
operation over all process, temperature, and voltage
variations. The benefits are smaller, lower power,
cleaner, reliable, and easy-to-use clock circuits.
2.1.1. Selectable Loop Filter Bandwidth
The digital characteristics of the DSPLL loop filter allow
control of the loop filter parameters without the need to
change external components. The Si5321 provides the
user with up to eight user-selectable loop bandwidth
settings for different system requirements. The base
loop bandwidth is selected using the BWSEL[1:0] pins
along with BWBOOST = 0 pins. When the BWBOOST
is driven high, the bandwidth selected on the
BWSEL[1:0] pins is doubled. (See Table 7.)
When the BWBOOST pin is asserted, the Si5321 shows
improved jitter generation performance. The BWBOOST
function is defined only when hitless recovery and FEC
scaling are disabled. Therefore, when BWBOOST is
high, the user must also drive FXDDELAY high and
FEC[1:0] to 000 for proper operation.
2.2. Clock Input and Output Rate Selection
The Si5321 provides a 1/32x, 1/16x, 1/8x, 1/4x, 1/2x,
1x, 2x, 4x, 8x, 16x, 32x, 64x, or 128x clock frequency
multiplication function with an option for additional
frequency scaling by a factor of 255/238, 238/255, 255/
237, 237/255, 66/64, or 64/66 for FEC rate compatibility.
Output rates vary in accordance with the input clock
rate. The multiplication factor is configured by selecting
the input and output clock frequency ranges for the
device.
The Si5321 accepts an input clock in the 19, 38, 77,
155, 311, or 622 MHz frequency range. The input
frequency range is selected using the INFRQSEL[2:0]
pins. The INFRQSEL[2:0] settings and associated
output clock rates are listed in Table 8.
The Si5321’s DSPLL phase locks to the clock input
signal to generate an internal VCO frequency that is a
multiple of the input clock frequency. The internal VCO
frequency is divided down to produce a clock output in
the 19, 39, 78, 155, 311, 622, 1250, or 2500 MHz
frequency range. The clock output range is selected
using the frequency select (FRQSEL[2:0]) pins. The
FRQSEL[2:0] settings and associated output clock rates
are given in Table 9.
Rev. 2.5
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