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SI5321 Datasheet, PDF (14/34 Pages) List of Unclassifed Manufacturers – SONET/SDH PRECISION CLOCK MULTIPLIER IC
Si5321
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD33 = 3.3 V ±5%, TA = –20 to 85 °C)
Parameter
Clock Output Wander with
Temperature Gradient 1,2
Symbol
CCO_TG
Initial Frequency Accuracy in Digital Hold CDH_FA
Mode (first 100 ms with voltage and
temperature held constant)
Clock Output Frequency Accuracy Over CDH_T
Temperature in Digital Hold Mode
Clock Output Frequency Accuracy Over
Supply Voltage in Digital Hold Mode
Clock Output Phase Step3(See Figure 8)
CDH_V33
tPT_MTIE
Clock Output Phase Step Slope3
mPT
(See Figure 8)
Test Condition
Stable Input Clock;
Temperature
Gradient <10 C/min;
800 Hz Loop BW
Stable Input Clock
Selected until entering
Digital Hold
Constant Supply Voltage
Constant Temperature
When hitlessly recovering
from Digital Hold mode
When hitlessly recovering
from Digital Hold mode
Min Typ Max Unit
— — 45 ps/
C/
min
— — 5.5 ppm
— 17.2 30 ppm
/C
— — 600 ppm
/V
–200 0 200 ps
BWSEL[1:0] = 11, BWBOOST = 0
BWSEL[1:0] = 00, BWBOOST = 0
BWSEL[1:0] = 01, BWBOOST = 0
BWSEL[1:0] = 10, BWBOOST = 0
6400 Hz, No Scaling
3200 Hz, No Scaling
1600 Hz, No Scaling
800 Hz, No Scaling
— — 10 ps/
— — 5 µs
— — 2.5
— — 1.25
Notes:
1. Higher PLL bandwidth settings provide smaller clock output wander with temperature gradient.
2. For reliable device operation, temperature gradients should be limited to 10 °C/min.
3. Telcordia GR-1244-CORE requirements specify maximum phase transient slope during clock rearrangement in terms
of nanoseconds per millisecond. The equivalent ps/s unit is used here since the maximum phase transient magnitude
for the Si5321 (tPT_MTIE) never reaches one nanosecond.
14
Rev. 2.5