SI53152 Datasheet, PDF (6/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53152
Table 2. AC Electrical Specifications (Continued)
Parameter
Rising/Falling Slew Rate
Symbol
T_R / T_F
Test Condition
Measured differentially from
±150 mV
Min Typ Max Unit
2.5
—
8 V/ns
Crossing Point Voltage at 0.7 V
V_OX
Swing
Enable/Disable and Set-Up
300
—
550 mV
Clock Stabilization from
Power-up
T_STABLE
—
—
Stopclock Set-up Time
T_SS
10.0
—
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
5 ms
— ns
Table 3. Absolute Maximum Conditions
Parameter
Main Supply Voltage
Input Voltage
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Symbol
V_{DD_3.3V}
V_IN
T_S
T_A
T_J
Ø_JC
Ø_JA
ESD_HBM
UL-94
Test Condition
Functional
Min Typ
—
—
Relative to V_SS
Non-functional
–0.5 —
–65 —
Functional
–40 —
Functional
—
—
JEDEC (JESD 51)
—
—
JEDEC (JESD 51)
—
—
JEDEC (JESD 22-A114) 2000 —
UL (Class)
V–0
Max Unit
4.6 V
4.6 V_DC
150 °C
85 °C
150 °C
35 °C/W
37 °C/W
—V
Note: While using multiple power supplies, the voltage on any input or I/O pin cannot exceed the power pin during power-up.
Power supply sequencing is not required.
6
Rev. 1.1