SI53152 Datasheet, PDF (1/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53152
PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4
FANOUT BUFFER
Features
 PCI-Express Gen 1, Gen 2, Gen 3,  Dedicated output enable pin for
and Gen 4 common clock
each clock
compliant
 Two PCI-Express buffered clock
 Supports Serial ATA (SATA) at
outputs
100 MHz
 Supports LVDS outputs
 100–210 MHz operation
 I²C support with readback
 Low power, push pull, differential
capabilities
output buffers
 Extended temperature:
 Internal termination for maximum
–40 to 85 ^oC
integration
 3.3 V Power supply
 24-pin QFN package
Applications
Ordering Information:
See page 17
 Network attached storage
 Multi-function Printer
 Wireless access point
 Routers
Pin Assignments
Description
The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source
two PCIe clocks simultaneously. The device has two hardware output enable
inputs for enabling the respective differential outputs on the fly. The device
also features output enable control through I²C communication. I²C
programmability is also available to dynamically control skew, edge rate and
amplitude on the true, compliment, or both differential signals on the clock
outputs. This control feature enables optimal signal integrity as well as
optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for
free at www.silabs.com/pcie-learningcenter.
VDD 1
NC 2
VDD 3
VSS 4
OE_DIFF0* 5
VDD 6
24 23 22 21 20 19
18 OE_DIFF1*
17 VDD
25
GND
16 DIFF1
15 DIFF1
14 DIFF0
13 DIFF0
7 8 9 10 11 12
*Note: Internal 100 kohm pull-up.
Patents pending
Functional Block Diagram
DIFFIN
DIFFIN
SCLK
SDATA
OE [1:0]
Control & Memory
Control RAM
DIFF0
DIFF1
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53152