SI53152 Datasheet, PDF (5/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53152
Table 2. AC Electrical Specifications
Parameter
Symbol
Test Condition
Min Typ Max Unit
DIFFIN at 0.7 V
Input Frequency Range
f_in
100
—
210 MHz
Rising and Falling Slew Rates for T_R / T_F
Single ended measurement:
0.6
—
Each Clock Output Signal in a
V_OL = 0.175 to V_OH = 0.525 V
Given Differential Pair
(Averaged)
4 V/ns
Differential Input High Voltage
V_IH
Differential Input Low Voltage
V_IL
Crossing Point Voltage at 0.7 V
V_OX
Swing
Single-ended measurement
150
—
— mV
—
— –150 mV
250
—
550 mV
Vcross Variation over all edges
Differential Ringback Voltage
Time before ringback allowed
Absolute Maximum Input
Voltage
V_OX
V_RB
T_STABLE
V_MAX
Single-ended measurement
—
—
–100 —
500
—
—
140 mV
100 mV
— ps
1.15 V
Absolute Minimum Input
Voltage
V_MIN
–0.3
—
—
V
Duty Cycle for Each Clock
Output Signal in a Given
Differential Pair
Rise/Fall Matching
DIFF at 0.7 V
T_DC
Measured at crossing point V_OX 45
—
55 %
T_RFM
Determined as a fraction of
2 x (T_R – T_F)/(T_R + T_F)
—
—
20 %
Duty Cycle
Clock Skew
Additive Peak Jitter
T_DC
T_SKEW
Pk-Pk
Measured at 0 V differential
Measured at 0 V differential
45
—
55 %
—
—
50 ps
0
—
10 ps
Additive PCIe Gen 2
Phase Jitter
RMS_GEN2
10 kHz < F < 1.5 MHz
1.5 MHz< F < Nyquist Rate
0
—
0.5 ps
0
—
0.5 ps
Additive PCIe Gen 3
Phase Jitter
RMS_GEN3
Includes PLL BW 2–4 MHz
(CDR = 10 MHz)
0
—
0.10 ps
Additive PCIe Gen 4 Phase Jitter RMS_GEN4
PCIe Gen 4
—
Additive Cycle to Cycle Jitter
T_CCJ
Measured at 0 V differential
—
Long Term Accuracy
L_ACC
Measured at 0 V differential
—
Notes:
1. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
2. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
—
0.10 ps
—
50 ps
—
100 ppm
Rev. 1.1
5