SI53152 Datasheet, PDF (16/22 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER

Si53152
Pin #
16
17
18
19
20
21
22
23
24
25
Table 6. Si53152 24-Pin QFN Descriptions (Continued)
Name
DIFF1
Type
Description
O, DIF 0.7 V, 100 MHz differential clock.
VDD
OE_DIFF1
SCLK
SDATA
VDD
PWR 3.3 V power supply.
I,PU Active high input pin enables DIFF1 (internal 100 k pull-up).
Refer to Table 1 on page 4 for OE specifications.
I SMBus compatible SCLOCK.
I/O SMBus compatible SDATA.
PWR 3.3 V power supply.
DIFFIN
DIFFIN
VSS
I 0.7 V Differential True Input, typically 100 MHz. Input frequency range
100 to 210 MHz.
O 0.7 V Differential Complement Input, typically 100 MHz. Input frequency
range 100 to 210 MHz.
GND Ground.
GND
GND Ground for bottom pad of the IC.
16
Rev. 1.1