SI510-11 Datasheet, PDF (6/26 Pages) Silicon Laboratories – 2 to 4 week lead times

Si510/511
Table 3. Output Clock Levels and Symmetry
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC
Parameter
CMOS Output Logic
High
CMOS Output Logic
Low
CMOS Output Logic
High Drive
Symbol
V_OH
V_OL
I_OH
Test Condition
3.3 V
2.5 V
Min
0.85 x V_DD
—
–8
–6
1.8 V
–4
CMOS Output Logic
Low Drive
I_OL
3.3 V
8
2.5 V
6
CMOS Output Rise/Fall
Time
(20 to 80% V_DD)
LVPECL Output
Rise/Fall Time
(20 to 80% VDD)
HCSL Output Rise/Fall
Time (20 to 80% VDD)
LVDS Output Rise/Fall
Time (20 to 80% VDD)
LVPECL Output
Common Mode
LVPECL Output Swing
LVDS Output Common
Mode
LVDS Output Swing
HCSL Output Common
Mode
HCSL Output Swing
Duty Cycle
T_R/T_F
T_R/T_F
1.8 V
0.1 to 212.5 MHz,
C_L = 15 pF
0.1 to 212.5 MHz,
C_L = no load
T_R/T_F
T_R/T_F
V_OC
50  to V_DD – 2 V,
single-ended
V_O
50  to V_DD – 2 V,
single-ended
V_OC
100  line-line
V_DD = 3.3/2.5 V
100  line-line, V_DD = 1.8 V
V_O Single-ended, 100 differential
termination
V_OC
50 to ground
V_O
Single-ended
DC
All formats
4
0.45
0.3
100
100
350
—
0.55
1.13
0.83
0.25
0.35
0.58
48
Typ
—
—
—
—
—
—
—
—
0.8
0.6
—
—
—
V_DD –
1.4 V
0.8
1.23
0.92
0.35
0.38
0.73
50
Max
Unit
—
V
0.15 x V_DD V
—
mA
—
mA
—
mA
—
mA
—
mA
—
mA
1.2
ns
0.9
ns
565
ps
470
ps
800
ps
—
V
0.90
1.33
V_PPSE
V
1.00
0.45
0.42
0.85
52
V
V_PPSE
V
V_PPSE
%
6
Rev. 1.2