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SI510-11 Datasheet, PDF (24/26 Pages) Silicon Laboratories – 2 to 4 week lead times | |||
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Si510/511
DOCUMENT CHANGE LIST
Revision 0.9 to Revision 1.0
ï® Updated Table 1 on page 4.
ï¬ï Updates to supply current typical and maximum values
for CMOS, LVDS, LVPECL and HCSL.
ï¬ï CMOS frequency test condition corrected to 100 MHz.
ï¬ï Updates to OE VIH minimum and VIL maximum values.
ï® Updated Table 2 on page 5.
ï¬ï Dual CMOS nominal frequency maximum added.
ï¬ï Total stability footnotes clarified for 10 year aging at
40 °C.
ï¬ï Disable time maximum values updated.
ï¬ï Enable time parameter added.
ï® Updated Table 3 on page 6.
ï¬ï CMOS output rise / fall time typical and maximum
values updated.
ï¬ï LVPECL/HCSL output rise / fall time maximum value
updated.
ï¬ï LVPECL output swing maximum value updated.
ï¬ï LVDS output common mode typical and maximum
values updated.
ï¬ï HCSL output swing maximum value updated.
ï¬ï Duty cycle minimum and maximum values tightened to
48/52%.
ï® Updated Table 4 on page 7.
ï¬ï Phase jitter test condition and maximum value updated.
ï¬ï Phase noise typical values updated.
ï¬ï Additive RMS jitter due to external power supply noise
typical values updated.
ï¬ï Footnote 3 updated limiting the VDD to 2.5/3.3V
ï® Added Tables 5, 6, 7 for LVDS, HCSL, CMOS, and
Dual CMOS operations.
ï® Moved Absolute Maximum Ratings table.
ï® Added note to Figure 2 clarifying CMOS and Dual
CMOS maximum frequency.
ï® Updated Figure 10 outline diagram to correct pinout.
Revision 1.0 to Revision 1.1
ï® Updated Table 3.
ï¬ï CMOS Output Rise/Fall Time Test Condition updated.
Revision 1.1 to Revision 1.2
ï® Updated Table 3.
ï¬ï Separated LVPECL and HCSL output Rise/Fall time
specs.
ï¬ï Min Rise/Fall times added.
24
Rev. 1.2
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