SI510-11 Datasheet, PDF (10/26 Pages) Silicon Laboratories – 2 to 4 week lead times

Si510/511
Table 7. Output Clock Jitter and Phase Noise (CMOS, Dual CMOS (Complementary))
V_DD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, T_A = –40 to +85 ^oC; Output Format = CMOS, Dual CMOS (Complementary)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Phase Jitter
(RMS)
φJ
1.875 MHz to 20 MHz integration
—
0.25
0.35
ps
bandwidth² (brickwall)
Phase Noise,
156.25 MHz
12 kHz to 20 MHz integration band-
—
width² (brickwall)
φN
100 Hz
—
1 kHz
—
0.8
–86
–108
1.0
ps
—
dBc/Hz
—
dBc/Hz
10 kHz
—
–115
—
dBc/Hz
100 kHz
—
–123
—
dBc/Hz
Spurious
SPR
1 MHz
LVPECL output, 156.25 MHz,
offset>10 kHz
—
–136
—
dBc/Hz
—
–75
—
dBc
Notes:
1. Applies to output frequencies: 74.17582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25,
212.5 MHz.
2. Applies to output frequencies: 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 MHz.
Table 8. Environmental Compliance and Package Information
Mechanical Shock
Parameter
Mechanical Vibration
Solderability
Gross and Fine Leak
Resistance to Solder Heat
Moisture Sensitivity Level
Contact Pads
Conditions/Test Method
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 2003
MIL-STD-883, Method 1014
MIL-STD-883, Method 2036
MSL 1
Gold over Nickel
10
Rev. 1.2