SI510-11 Datasheet, PDF (12/26 Pages) Silicon Laboratories – 2 to 4 week lead times

Si510/511
2. Pin Descriptions
OE 1
4 VDD
NC 1
6 VDD
OE 1
6 VDD
OE 2
5 CLK–*
NC 2
5 CLK–*
GND 2
3 CLK
GND 3
4 CLK+
GND 3
4 CLK+
Si510 (CMOS)
Si510 (LVDS/LVPECL/HCSL/Dual CMOS*) Si511 (LVDS/LVPECL/HCSL/DualCMOS)*)
*Supports integrated 1:2 CMOS buffer. See ordering information and section 2.1“Dual CMOS Buffer”.
Table 11. Si510 Pin Descriptions (CMOS)
Pin
Name
CMOS Function
1
OE
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
2
GND
Electrical and Case Ground.
3
CLK
Clock Output.
4
V_DD
Power Supply Voltage.
Table 12. Si510 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 2)
Pin
Name
LVPECL/LVDS/HCSL Function
1
NC
No connect. Make no external connection to this pin.
2
OE
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6
V_DD
Power Supply Voltage.
Table 13. Si511 Pin Descriptions (LVPECL/LVDS/HCSL, Dual CMOS, OE Pin 1)
Pin
Name
LVPECL/LVDS/HCSL Function
1
OE
Output Enable. Includes internal pull-up for OE active high. Includes
internal pull-down for OE active low. See ordering information.
2
NC
No connect. Make no external connection to this pin.
3
GND
Electrical and Case Ground.
4
CLK+
Clock Output.
5
CLK–
Complementary Clock Output.
6
V_DD
Power Supply Voltage.
12
Rev. 1.2