SI52143 Datasheet, PDF (5/21 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK

Si52143
Table 2. AC Electrical Specification
Parameter
Crystal
Symbol
Test Condition
Min
Long-term Accuracy
Clock Input
L_ACC
Measured at VDD/2 differential —
Duty Cycle
CLKIN Rising and Falling Slew
Rate
Cycle to Cycle Jitter
Long Term Jitter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
DIFF at 0.7 V
T_DC
T_R/T_F
T_CCJ
T_LTJ
V_IH
V_IL
I_IH
I_IL
Measured at VDD/2
45
Measured between 0.2 V_DD and 0.5
0.8 V_DD
Measured at VDD/2
—
Measured at VDD/2
—
XIN/CLKIN pin
2
XIN/CLKIN pin
—
XIN/CLKIN pin, VIN = VDD
—
XIN/CLKIN pin, 0 < VIN <0.8
–35
Duty Cycle
Output-to-Output Skew
Cycle to Cycle Jitter
PCIe Gen 1 Pk-Pk Jitter,
Common Clock
PCIe Gen 2 Phase Jitter,
Common Clock
T_DC
T_SKEW
T_CCJ
Pk-Pk
RMS_GEN2
Measured at 0 V differential
45
Measured at 0 V differential
—
Measured at 0 V differential
—
PCIe Gen 1
0
10 kHz < F < 1.5 MHz
0
1.5 MHz< F < Nyquist Rate
0
PCIe Gen 3 Phase Jitter,
Common Clock
RMS_GEN3
PLL BW of 2–4 or 2–5 MHz,
0
CDR = 10 MHz
PCIe Gen 3 Phase Jitter,
Separate Reference No
Spread, SRNS
PCIe Gen 4 Phase Jitter,
Common Clock
RMS_{GEN3_SRNS} PLL BW of 2–4 or 2–5 MHz,
—
CDR = 10 MHz
RMS_GEN4
PLL BW of 2–4 or 2–5 MHz,
—
CDR = 10 MHz
Long Term Accuracy
Rising/Falling Slew Rate
L_ACC
T_R / T_F
Measured at 0 V differential
—
Measured differentially from
1
±150 mV
Voltage High
V_HIGH
—
Voltage Low
V_LOW
–0.3
Crossing Point Voltage at 0.7 V
V_OX
300
Swing
Notes:
1. Visit www.pcisig.com for complete PCIe specifications.
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.
Typ Max Unit
—
250 ppm
—
55
%
—
4.0 V/ns
—
250 ps
—
350 ps
— VDD+0.3 V
—
0.8
V
—
35
µA
—
—
µA
—
55
%
—
50
ps
35
50
ps
40
50
ps
2
2.6
ps
2
2.6
ps
0.5
0.9
ps
0.35 0.64 ps
0.5
0.9
ps
—
100 ppm
—
8
V/ns
—
1.15
V
—
—
V
—
550 mV
Rev 1.3
5