SI52143 Datasheet, PDF (17/21 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK

Pin #
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Si52143
Table 7. Si52143 24-Pin QFN Descriptions (Continued)
Name
DIFF1
VDD_DIFF
DIFF2
DIFF2
DIFF3
DIFF3
VDD_DIFF
OE[3:2]
SCLK
SDATA
VDD_CORE
XOUT
XIN/CLKIN
VSS_CORE
GND
Type
Description
O, DIF 0.7 V, 100 MHz differential clock output.
PWR 3.3 V power supply.
O, DIF 0.7 V, 100 MHz differential clock output.
O, DIF 0.7 V, 100 MHz differential clock output.
O, DIF 0.7 V, 100 MHz differential clock output.
O, DIF 0.7 V, 100 MHz differential clock output.
PWR 3.3 V power supply.
I,PU Active high input to enable or disable DIFF2 and DIFF3 clocks.
I I²C SCLOCK.
I/O I²C SDATA.
PWR 3.3 V power supply.
O 25.00 MHz crystal output, Float XOUT if using only CLKIN (Clock input).
I 25.00 MHz crystal input or 3.3 V, 25 MHz Clock Input.
GND Ground.
GND Ground for bottom pad of the IC.
Rev 1.3
17