SI52143 Datasheet, PDF(1/21 Page) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK

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SI52143 Datasheet, PDF (1/21 Pages) Silicon Laboratories – PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK

Si52143

PCI-EXPRESS GEN 1, GEN 2, & GEN 3 QUAD OUTPUT

CLOCK GENERATOR WITH 25 MHZ REFERENCE CLOCK

Features

ï® PCI-Express Gen 1, Gen 2, Gen 3, ï® Four PCI-Express clocks

and Gen 4 common clock compliant ï® 25 MHz reference clock output

ï® Gen 3 SRNS Compliant

ï® 25 MHz crystal input or clock input

ï® Supports Serial ATA (SATA) at

ï® Signal integrity tuning

100 MHz

ï® I2C support with readback

ï® Low power, push-pull HCSL

capabilities

compatible differential outputs

ï® Triangular spread spectrum profile

ï® No termination resistors required

for maximum electromagnetic

ï® Dedicated output enable hardware

interference (EMI) reduction

pins for each clock output

ï® Spread enable pin on differential

clocks

ï® Industrial temperature

â40 to 85 oC

ï® 3.3 V power supply

ï® 24-pin QFN package

Applications

ï® Network attached storage

ï® Multi-function printer

ï® Wireless access point

ï® Routers

Description

The Si52143 is a spread-spectrum enabled PCIe clock generator that can source

four PCIe clocks and a 25 MHz reference clock. The device has three hardware

output enable pins for enabling the outputs (on the fly while powered on), and one

hardware pin to control spread spectrum on PCIe clock outputs. In addition to the

hardware control pins, I2C programmability is also available to dynamically control

skew, edge rate and amplitude on the true, compliment, or both differential signals

on the PCIe clock outputs. This control feature enables optimal signal integrity as

well as optimal EMI signature on the PCIe clock outputs. Refer to AN636 for

signal integrity tuning and configurability. Measuring PCIe clock jitter is quick and

easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at

www.silabs.com/pcie-learningcenter.

Functional Block Diagram

Ordering Information:

See page 18

Pin Assignments

VDD_REF 1

REF 2

SSON2 3

VSS_REF 4

OE_REF1 5

VDD_DIFF 6

24 23 22 21 20 19

18 OE[3:2]1

17 VDD_DIFF

GND

16 DIFF3

15 DIFF3

14 DIFF2

13 DIFF2

7 8 9 10 11 12

Notes:

1. Internal 100 kohm pull-up.

2. Internal 100 kohm pull-down.

Patents pending

XIN/CLKIN

XOUT

SCLK

SDATA

OE_REF

OE [1:0]

OE [3:2]

SSON

PLL

(SSC)

Control & Memory

Control RAM

Divider

REF

DIFF0

DIFF1

DIFF2

DIFF3

Rev 1.3 12/15

Si52143

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