SI4468-7 Datasheet, PDF (49/57 Pages) Silicon Laboratories – Highly configurable packet handler

Si4468/7
Pin Pin Name
I/0
Description
12
SCLK
Serial Clock Input.
I
0–VDD V digital input. This pin provides the serial data clock function for the
4-line serial data bus. Data is clocked into the Si446x on positive edge transi-
tions.
13
SDO
O
0–VDD V Digital Output.
Provides a serial readback function of the internal control registers.
14
SDI
Serial Data Input.
I _{0–VDD V digital input. This pin provides the serial data stream for the 4-line}
serial data bus.
15
nSEL
Serial Interface Select Input.
I _{0–VDD V digital input. This pin provides the Select/Enable function for the}
4-line serial data bus.
16
XOUT
Crystal Oscillator Output.
O _{Connect to an external 25 to 32 MHz crystal, or leave floating when driving}
with an external source on XIN.
17
XIN
18
GND
19
GPIO2
20
GPIO3
PKG PADDLE_GND
I
GND
Crystal Oscillator Input.
Connect to an external 25 to 32 MHz crystal, or connect to an external source.
When using an XTAL, leave floating per the reference design schematic. When
using a TCXO, connect to TCXO GND, which should be separate from the
board’s reference ground plane.
I/O
I/O
GND
General Purpose Digital I/O.
May be configured through the registers to perform various functions, including
Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery
Detect, TRSW, AntDiversity control, etc.
The exposed metal paddle on the bottom of the Si446x supplies the RF and cir-
cuit ground(s) for the entire chip. It is very important that a good solder connec-
tion is made between this exposed metal paddle and the ground plane of the
PCB underlying the Si446x.
Rev 1.0
49